2004年04月14日

VHDLはじめました

「FPGAボードで学ぶ論理回路設計」で遊んでいます。 カウンタを2桁にしてみようとしましたが・・・
前回はカウンタ(LED表示)が1桁でしたが、それを2桁にしてみました。 とりあえず動いています。が、その方法は、単純にコードをコピーしています。もしこれがソフトウェアなら、こんなプログラムを書く人を私は信用できません(^^;)。 とは言うものの、今のレベルはこんなものなので、ちゃんと書く方法はおいおい調べることにしましょう。
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity test8 is
	port (
		sw_in: in  std_logic;
		reset_in: in  std_logic;
		clk: in  std_logic;
		led_out1: out std_logic_vector(7 downto 0);
		led_out2: out std_logic_vector(7 downto 0)
	);
end test8;

architecture rtl of test8 is
signal counter1: std_logic_vector(3 downto 0);
signal counter2: std_logic_vector(3 downto 0);
signal sec_clk: integer range 0 to (330000-1);
signal older_sw: std_logic;
signal oldest_sw: std_logic;
signal prev_state: std_logic;
begin
	process (clk)
	begin
		if clk'event and clk = '1' then
			sec_clk <= sec_clk + 1;
			if sec_clk = 0 then
				oldest_sw <= older_sw;
				older_sw <= sw_in;
			end if;
		end if;
	end process;

	process (clk, reset_in)
	begin
		if reset_in = '0' then
			counter1 <= "0000";
			counter2 <= "0000";
		elsif clk'event and clk = '1' then
			if sw_in = '0' and older_sw = '0' and oldest_sw = '0' then
				if prev_state = '1' then
					prev_state <= '0';
					if counter1 = 9 then
						counter1 <= "0000";
						if counter2 = 9 then
							counter2 <= "0000";
						else
							counter2 <= counter2 + 1;
						end if;
					else
						counter1 <= counter1 + 1;
					end if;
				end if;
			else
				prev_state <= '1';
			end if;
		end if;
	end process;
		
	process (counter1)
	begin
		case counter1 is
			when "0000" => led_out1 <= "00000011";
			when "0001" => led_out1 <= "10011111";
			when "0010" => led_out1 <= "00100101";
			when "0011" => led_out1 <= "00001101";
			when "0100" => led_out1 <= "10011001";
			when "0101" => led_out1 <= "01001001";
			when "0110" => led_out1 <= "01000001";
			when "0111" => led_out1 <= "00011111";
			when "1000" => led_out1 <= "00000001";
			when "1001" => led_out1 <= "00001001";
			when "1010" => led_out1 <= "00010001";
			when "1011" => led_out1 <= "11000001";
			when "1100" => led_out1 <= "11100101";
			when "1101" => led_out1 <= "10000101";
			when "1110" => led_out1 <= "01100001";
			when "1111" => led_out1 <= "01110001";
			when others => led_out1 <= "11111110";
		end case;
	end process;
		
	process (counter2)
	begin
		case counter2 is
			when "0000" => led_out2 <= "00000011";
			when "0001" => led_out2 <= "10011111";
			when "0010" => led_out2 <= "00100101";
			when "0011" => led_out2 <= "00001101";
			when "0100" => led_out2 <= "10011001";
			when "0101" => led_out2 <= "01001001";
			when "0110" => led_out2 <= "01000001";
			when "0111" => led_out2 <= "00011111";
			when "1000" => led_out2 <= "00000001";
			when "1001" => led_out2 <= "00001001";
			when "1010" => led_out2 <= "00010001";
			when "1011" => led_out2 <= "11000001";
			when "1100" => led_out2 <= "11100101";
			when "1101" => led_out2 <= "10000101";
			when "1110" => led_out2 <= "01100001";
			when "1111" => led_out2 <= "01110001";
			when others => led_out2 <= "11111110";
		end case;
	end process;
end rtl;
---